DSP • 5-stage assembly line, maximum working frequency 160MHz; • 32bit / 16bit multiplication: MAC16, mul16, mul32; • 32bit integer division; • single precision floating point operation; • dedicated hardware audio acceleration engine; • 32KB instruction cache, 32KB data cache, supporting WB / wt; • integrated local SRAM; MCU • high performance Cortex-M0, maximum working frequency 80MHz; • built in 8KB cache, which is divided into four address areas, and whether the cache is configured independently; • support frequency reduction, with a maximum bus frequency of one quarter